Views:104
Applicants:6
Posted on 13 Jun, 2025
1) Should be comfortable with Vivado
2) Coding language: VHDL/Verilog/SystemVerilog
3) Should have developed AXI peripherals for Zynq and other Xilinx FPGAs. Should have a knowledge of the PS and PL parts
4) Should know how to implement timing and other constraints
5) Should know how to interface external memory using the EMC in Vivado